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mosfet metaloxidesemiconductorfieldeffecttransistor optimos tm optimos tm fdpower-transistor ,200v IPB117N20NFD datasheet rev.2.0 final powermanagement&multimarket
2 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet d2pak 1description features ?n-channel,normallevel ?fastdiode(fd)withreducedq rr ?optimizedforhardcommutationruggedness ?verylowon-resistance r ds(on) ?175coperatingtemperature ?pb-freeleadplating;rohscompliant ?qualifiedaccordingtojedec 1) fortargetapplication ?halogen-freeaccordingtoiec61249-2-21 table1keyperformanceparameters parameter value unit v ds 200 v r ds(on),max 11.7 m w i d 84 a type/orderingcode package marking relatedlinks IPB117N20NFD pg-to 263-3 117n20nf - 1) j-std20 and jesd22 drain pin 2, tab gate pin 1 source pin 3
3 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet tableofcontents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 drain pin 2, tab gate pin 1 source pin 3
4 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet 2maximumratings at t j =25c,unlessotherwisespecified table2maximumratings at 25 c values min. typ. max. parameter symbol unit note/testcondition continuous drain current i d - - - - 84 60 a t c =25c t c =100c pulsed drain current 1) i d,pulse - - 336 a t c =25c avalanche energy, single pulse e as - - 375 mj i d =67a, r gs =25 w reversediodepeakd v /d t d v /d t - - 60 kv/s i d =160a, v ds =100v, d i /d t =1500a/s, t j,max =175c gate source voltage v gs -20 - 20 v - power dissipation p tot - - 300 w t c =25c operating and storage temperature t j , t stg -55 - 175 c iec climatic category; din iec 68-1: 55/175/56 3thermalcharacteristics table3thermalcharacteristics values min. typ. max. parameter symbol unit note/testcondition thermal resistance, junction - case r thjc - 0.3 0.5 k/w - thermal resistance, junction - ambient, minimal footprint r thja - - 62 k/w - thermal resistance, junction - ambient, 6 cm 2 cooling area 2) r thja - - 40 k/w - 1) see figure 3 2) device on 40 mm x 40 mm x 1.5 mm epoxy pcb fr4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. pcb is vertical in still air. drain pin 2, tab gate pin 1 source pin 3
5 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet 4electricalcharacteristics table4staticcharacteristics values min. typ. max. parameter symbol unit note/testcondition drain-source breakdown voltage v (br)dss 200 - - v v gs =0v, i d =1ma gate threshold voltage v gs(th) 2 3 4 v v ds = v gs , i d =270a zero gate voltage drain current i dss - - 0.1 10 1 100 a v ds =160v, v gs =0v, t j =25c v ds =160v, v gs =0v, t j =125c gate-source leakage current i gss - 1 100 na v gs =20v, v ds =0v drain-source on-state resistance r ds(on) - 10.3 11.7 m w v gs =10v, i d =84a gate resistance r g - 2.4 3.6 w - transconductance g fs 70 139 - s | v ds |>2| i d | r ds(on)max , i d =84a table5dynamiccharacteristics values min. typ. max. parameter symbol unit note/testcondition input capacitance c iss - 5000 6650 pf v gs =0v, v ds =100v, f =1mhz output capacitance c oss - 400 532 pf v gs =0v, v ds =100v, f =1mhz reverse transfer capacitance c rss - 6 13 pf v gs =0v, v ds =100v, f =1mhz turn-on delay time t d(on) - 13 - ns v dd =100v, v gs =10v, i d =42a, r g,ext =1.6 w rise time t r - 10 - ns v dd =100v, v gs =10v, i d =42a, r g,ext =1.6 w turn-off delay time t d(off) - 24 - ns v dd =100v, v gs =10v, i d =42a, r g,ext =1.6 w fall time t f - 8 - ns v dd =100v, v gs =10v, i d =42a, r g,ext =1.6 w table6gatechargecharacteristics 1) values min. typ. max. parameter symbol unit note/testcondition gate to source charge q gs - 25 - nc v dd =100v, i d =84a, v gs =0to10v gate to drain charge q gd - 8 - nc v dd =100v, i d =84a, v gs =0to10v switching charge q sw - 17 - nc v dd =100v, i d =84a, v gs =0to10v gate charge total q g - 65 87 nc v dd =100v, i d =84a, v gs =0to10v gate plateau voltage v plateau - 4.7 - v v dd =100v, i d =84a, v gs =0to10v output charge q oss - 162 - nc v dd =100v, v gs =0v 1) see 2 gate charge waveforms 2 for parameter definition drain pin 2, tab gate pin 1 source pin 3
6 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet table7reversediode values min. typ. max. parameter symbol unit note/testcondition diode continous forward current i s - - 84 a t c =25c diode pulse current 1) i s,pulse - - 336 a t c =25c diode hard commutation current 2) i s,hard - - 160 a t c =25c, d i f /d t =1500a/s diode forward voltage v sd - 1 1.2 v v gs =0v, i f =84a, t j =25c reverse recovery time t rr - 144 288 ns v r =100v, i f =56a,d i f /d t =100a/s reverse recovery charge q rr - 629 - nc v r =100v, i f =56a,d i f /d t =100a/s 1) diode pulse current is defined by thermal and/or package limits 2) maximum allowed hard-commutated current through diode at di/dt=1500 a/s drain pin 2, tab gate pin 1 source pin 3
7 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet 5electricalcharacteristicsdiagrams diagram1:powerdissipation t c [c] p tot [w] 0 50 100 150 200 0 40 80 120 160 200 240 280 320 p tot =f( t c ) diagram2:draincurrent t c [c] i d [a] 0 50 100 150 200 0 20 40 60 80 100 i d =f( t c ); v gs 3 10v diagram3:safeoperatingarea v ds [v] i d [a] 10 -1 10 0 10 1 10 2 10 3 10 -1 10 0 10 1 10 2 10 3 1 s 10 s 100 s 1 ms 10 ms dc i d =f( v ds ); t c =25c; d =0;parameter: t p diagram4:max.transientthermalimpedance t p [s] z thjc [k/w] 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 -2 10 -1 10 0 0.5 0.2 0.1 0.05 0.02 0.01 single pulse z thjc =f( t p );parameter: d = t p / t drain pin 2, tab gate pin 1 source pin 3
8 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet diagram5:typ.outputcharacteristics v ds [v] i d [a] 0 1 2 3 4 5 0 25 50 75 100 125 150 175 200 10 v 7 v 5 v 4.5 v i d =f( v ds ); t j =25c;parameter: v gs diagram6:typ.drain-sourceonresistance i d [a] r ds(on) [m w ] 0 20 40 60 80 100 120 140 0 5 10 15 20 4.5 v 5 v 7 v 10 v r ds(on) =f( i d ); t j =25c;parameter: v gs diagram7:typ.transfercharacteristics v gs [v] i d [a] 0 2 4 6 8 0 20 40 60 80 100 120 140 160 180 200 175 c 25 c i d =f( v gs );| v ds |>2| i d | r ds(on)max ;parameter: t j diagram8:typ.forwardtransconductance i d [a] g fs [s] 0 25 50 75 100 125 150 0 20 40 60 80 100 120 140 160 180 g fs =f( i d ); t j =25c drain pin 2, tab gate pin 1 source pin 3
9 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet diagram9:drain-sourceon-stateresistance t j [c] r ds(on) [m w ] -60 -20 20 60 100 140 180 0 5 10 15 20 25 30 35 98% typ r ds(on) =f( t j ); i d =84a; v gs =10v diagram10:typ.gatethresholdvoltage t j [c] v gs(th) [v] -60 -20 20 60 100 140 180 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2700 a 270 a v gs(th) =f( t j ); v gs = v ds ;parameter: i d diagram11:typ.capacitances v ds [v] c [pf] 0 40 80 120 160 10 0 10 1 10 2 10 3 10 4 ciss coss crss c =f( v ds ); v gs =0v; f =1mhz diagram12:forwardcharacteristicsofreversediode v sd [v] i f [a] 0.0 0.5 1.0 1.5 2.0 10 0 10 1 10 2 10 3 25 c 175 c 25c, 98% 175c, 98% i f =f( v sd );parameter: t j drain pin 2, tab gate pin 1 source pin 3
10 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet diagram13:avalanchecharacteristics t av [s] i as [a] 10 0 10 1 10 2 10 3 10 0 10 1 10 2 25 c 100 c 125 c i as =f( t av ); r gs =25 w ;parameter: t j(start) diagram14:typ.gatecharge q gate [nc] v gs [v] 0 20 40 60 80 0 2 4 6 8 10 160 v 100 v 40 v v gs =f( q gate ); i d =84apulsed;parameter: v dd diagram15:drain-sourcebreakdownvoltage t j [c] v br(dss) [v] -60 -20 20 60 100 140 180 160 170 180 190 200 210 220 230 v br(dss) =f( t j ); i d =1ma drain pin 2, tab gate pin 1 source pin 3 gate charge waveforms
11 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet 6packageoutlines figure1outlinepg-to263-3,dimensionsinmm/inches drain pin 2, tab gate pin 1 source pin 3 gate charge waveforms
12 optimos tm fdpower-transistor ,200v IPB117N20NFD rev.2.0,2014-02-06 final data sheet revisionhistory IPB117N20NFD revision:2014-02-06,rev.2.0 previous revision revision date subjects (major changes since last revision) 2.0 2014-02-06 release of final version welistentoyourcomments anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com publishedby infineontechnologiesag 81726mnchen,germany ?2014infineontechnologiesag allrightsreserved. legaldisclaimer theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics.with respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication ofthedevice,infineontechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithout limitation,warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. information forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestinfineon technologiesoffice( www.infineon.com ). warnings duetotechnicalrequirements,componentsmaycontaindangeroussubstances.forinformationonthetypesinquestion, pleasecontactthenearestinfineontechnologiesoffice. theinfineontechnologiescomponentdescribedinthisdatasheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofinfineontechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. drain pin 2, tab gate pin 1 source pin 3 gate charge waveforms

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